Arrayed semiconductor device, optical transmission module, optical module, and method for manufacturing thereof

ABSTRACT

In the arrayed semiconductor optical device, a plurality of semiconductor optical devices including a first semiconductor optical device and a second semiconductor optical device are monolithically integrated on a semiconductor substrate, each of the semiconductor optical devices includes a first semiconductor layer having a multiple quantum well layer and a grating layer disposed on an upper side of the first semiconductor layer, a layer thickness of the first semiconductor layer of the first semiconductor optical device is thinner than a layer thickness of the first semiconductor layer of the second semiconductor optical device, and a height of the grating layer of the first semiconductor optical device is lower than a height of the grating layer of the second semiconductor optical device corresponding to difference in the layer thickness of the first semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese application JP2016-233431, filed on Nov. 30, 2016, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an arrayed semiconductor opticaldevice, an optical transmitter module, an optical module, and a methodfor manufacturing thereof, specifically, to a technique for reducingvariation in performance of devices between channels.

2. Description of the Related Art

An arrayed semiconductor optical device on which a plurality ofsemiconductor optical devices having mutually different emissionwavelengths are mounted is generally used. It is desired to realize bothlarge capacity and small size of the arrayed semiconductor opticaldevice. For such purpose, technique capable of increasing the number ofthe plurality of semiconductor optical devices (the number of channels)which are mounted on one arrayed semiconductor optical device andmounting the plurality of semiconductor optical devices in a small areais necessary.

In a fabrication of an arrayed semiconductor optical device, an arrayingmethod in which semiconductor optical devices having correspondingemission wavelengths are respectively fabricated by separate waferprocesses and are integrated in a hybrid manner at the time of mountingis widely used. In this case, since it is necessary to mount eachsemiconductor optical device individually, there is a limit to highdensity mounting considering a space required for the mounting.Additionally, the number of wafers corresponding to the number ofchannels is fabricated, which is also a problem from a viewpoint of costreduction.

On the other hand, monolithic integrated technique in which a pluralityof semiconductor optical devices can be simultaneously fabricated on onewafer by a common crystal growth process has been proposed. By usingthis method, a plurality of arrayed semiconductor optical devices inwhich a plurality of semiconductor optical devices having mutuallydifferent emission wavelengths are formed with device spacing of, forexample, about several hundred μm are fabricated on one wafer, and thereis a possibility that a size of the arrayed semiconductor optical deviceitself can be reduced. As an example of the monolithic integratedtechnique, there is a Selective-Area-Growth (SAG) method described in JP07-226563A.

In the monolithic integrated technique disclosed in JP H07-226563A, apair of insulator masks having different mask width and forming a pairof stripes is formed in regions in which a plurality of semiconductoroptical devices are formed using the Selective-Area-Growth effect byMetal-organic vapor phase epitaxy (MOVPE). As a result, since a layerthickness increases according to mask spacing and mask width andcomposition change occurs, multiple quantum well (MQW) layers havingmutually different emission wavelengths can be simultaneously formed onthe same wafer by a common crystal growth process. For example, as themask width increases, the group III atoms that have reached on the maskdiffuse more and an amount of those that contributes to growth in anopening between the masks increases. Thus, an increase rate of a layerthickness increases and larger change in a emission wavelength can becaused.

For example, in a case where each semiconductor optical device of anarrayed semiconductor optical device is composed of a distributedfeedback (DFB) laser, an arrayed semiconductor optical device in which aplurality of semiconductor optical devices having mutually differentemission wavelengths are integrated can be realized on the samesubstrate by changing a period of gratings on a wafer surface using onewafer having the same emission wavelength. However, differences(detuning) between emission wavelength of a semiconductor optical deviceand emission wavelength (gain peak) of MQW layer (active layer) in eachchannel vary for each semiconductor optical device in each channel, sothat there is large variation in performance of each semiconductoroptical device in one arrayed semiconductor optical device.

On the other hand, JP 07-226563A discloses that a plurality ofsemiconductor optical devices having desired emission wavelengths can berealized by one-time crystal growth process using the monolithicintegrated technique. A fabrication method using a method capable ofchanging an emission wavelength itself of an MQW layer like the SAGmethod is desirable in that detuning can be kept within a predeterminedrange.

In a case where each semiconductor optical device is a DFB laser,grating is provided in a semiconductor multilayer structure of eachsemiconductor optical device for making a single mode emission. In afabrication method of an arrayed semiconductor optical device using SAGmethod described in JP 07-226563A, the grating is formed in advance onthe substrate side of a MQW layer (active layer), or formed on the sideopposite to the substrate side of the MQW layer (active layer) by usinga grating layer that selectively grows in the same process as the MQWlayer. In the former (lower side grating), a crystallinity of the MQWlayer may be deteriorated due to an influence of unevenness of thegrating disposed on the lower side of the MQW layer. In the latter(upper side grating), the deterioration of the crystallinity seen in theformer is less likely to occur. In addition, it is possible to preciselydetermine a forming condition of the grating after confirming anemission wavelength of an MQW layer. Therefore, an arrayed semiconductoroptical device in which a plurality of semiconductor optical deviceshaving the upper side grating are monolithically integrated isdesirable.

However, when the MQW layer and the upper side grating is selectivelygrown in the same process, a layer thickness of the grating layerdiffers for each semiconductor optical device in each channel. As aresult of an intensive study by inventors, variation in performance ofthe semiconductor optical device in each channel may occur due to thedifference in the layer thickness of the grating layer.

SUMMARY OF THE INVENTION

The present invention has been made in view of such problems and anobject of the present invention is to provide an arrayed semiconductoroptical device realizing miniaturization of an optical transmittermodule and an optical module, and a method for manufacturing thereofwhile reducing variation in performance of semiconductor optical devicesbetween channels.

(1) In order to solve the above-mentioned problems, according to thepresent invention, there is provided an arrayed semiconductor opticaldevice in which a plurality of semiconductor optical devices including afirst semiconductor optical device and a second semiconductor opticaldevice are monolithically integrated on a semiconductor substrate, eachof the semiconductor optical devices includes a first semiconductorlayer having a multiple quantum well layer and a grating layer disposedon an upper side of the first semiconductor layer, a layer thickness ofthe first semiconductor layer of the first semiconductor optical deviceis thinner than a layer thickness of the first semiconductor layer ofthe second semiconductor optical device, and a height of the gratinglayer of the first semiconductor optical device is lower than a heightof the grating layer of the second semiconductor optical devicecorresponding to difference in the layer thickness of the firstsemiconductor layer.

(2) In the arrayed semiconductor optical device according to theabove-mentioned (1), the first semiconductor layer of each of thesemiconductor optical devices may further include a lower side opticalguide layer disposed in contact with a lower side of the multiplequantum well layer and an upper side optical guide layer disposed incontact with an upper side of the multiple quantum well layer.

(3) In the arrayed semiconductor optical device according to theabove-mentioned (2), the first semiconductor layer of each of thesemiconductor optical devices may be composed of the lower side opticalguide layer, the multiple quantum well layer, and the upper side opticalguide layer.

(4) In the arrayed semiconductor optical device according to any one ofthe above-mentioned (1) to (3), difference in heights between thegrating layer of the first semiconductor optical device and the gratinglayer of the second semiconductor optical device may be substantiallydue to difference in the layer thickness of the first semiconductorlayer.

(5) In the arrayed semiconductor optical device according to any one ofthe above-mentioned (1) to (4), each of the semiconductor opticaldevices may further include an etching stop layer disposed between thefirst semiconductor layer and the grating layer.

(6) According to the present invention, there may be provided an opticaltransmitter module including the arrayed semiconductors optical deviceaccording to any one of the above-mentioned (1) to (5).

(7) According to the present invention, there may be provided an opticalmodule including the optical transmitter module according to theabove-mentioned (6).

(8) According to the present invention, there is provided a method formanufacturing an arrayed semiconductor optical device including aplurality of semiconductor optical devices including a firstsemiconductor optical device and a second semiconductor optical devicewhich are monolithically integrated on a semiconductor substrate, eachof the semiconductor optical devices includes a first semiconductorlayer having multiple quantum well layer and a grating layer disposed onan upper side of the first semiconductor layer, the method may include afirst semiconductor layer deposition process of simultaneouslydepositing the first semiconductor layer of the first semiconductoroptical device and the first semiconductor layer of the secondsemiconductor optical device such that the layer thickness of the firstsemiconductor layer of the first semiconductor optical device is thinnerthan that of the first semiconductor layer of the second semiconductoroptical device; and a grating layer deposition process of simultaneouslydepositing the grating layer of the first semiconductor optical deviceand that of the second semiconductor optical device under commondeposition conditions.

(9) In the method for manufacturing the arrayed semiconductor opticaldevice according to the above-mentioned (8), in the first semiconductorlayer deposition process, the first semiconductor layer of the firstsemiconductor optical device and the first semiconductor layer of thesecond semiconductor optical device may simultaneously be deposited bySelective-Area-Growth.

The present invention may provide the arrayed semiconductor opticaldevice realizing miniaturization of the optical transmitter module andthe optical module, and the method for manufacturing thereof whilereducing variation in performance of semiconductor optical devicesbetween channels.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a configuration of an opticaltransmission device according to first embodiment of the invention.

FIG. 2 is a plan view illustrating a configuration of an opticaltransmitter module according to the first embodiment of the invention.

FIG. 3A is a schematic diagram illustrating a semiconductor multilayerstructure of a semiconductor optical device according to the firstembodiment of the invention.

FIG. 3B is a schematic diagram illustrating a semiconductor multilayerstructure of a semiconductor optical device according to the firstembodiment of the invention.

FIG. 4A is a schematic diagram illustrating a structure of an arrayedsemiconductor optical device according to the first embodiment of theinvention.

FIG. 4B is a detailed view of main portions of semiconductor multilayerstructures of the arrayed semiconductor optical device.

FIG. 5 is a graph illustrating an absolute value of a change rate ofcoupling coefficient K with respect to an increase rate of a layerthickness in a first semiconductor layer and a grating layer of asemiconductor optical device.

FIGS. 6A to 6L are diagrams illustrating processes of a manufacturingmethod of the arrayed semiconductor optical device according to thefirst embodiment of the invention.

FIG. 7 is a schematic diagram illustrating a structure of the arrayedsemiconductor optical device according to the second embodiment of theinvention.

FIG. 8 is a schematic diagram illustrating a structure of the arrayedsemiconductor optical device according to the third embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the invention will be described specificallyand in detail with reference to drawings. In all the drawings fordescribing the embodiments, the same reference numerals are assigned tomembers having the same function and repetitive description thereof willbe omitted. The following drawings merely illustrate examples of theembodiments, and sizes of the drawings and scales described in theexamples do not necessarily coincide with each other.

First Embodiment

FIG. 1 is a schematic diagram illustrating a configuration of an opticaltransmission device 101 according to the first embodiment of theinvention. A plurality of optical modules 102 are mounted on the opticaltransmission device 101. The optical transmission device 101 includes aprinted circuit board 111 and an IC 112. The optical transmission device101 is, for example, a large capacity router or a switch. The opticaltransmission device 101 has, for example, a function of a signalexchanger and is disposed in a base station or the like. The opticaltransmission device 101 acquires data for reception (electric signal forreception) from the optical module 102, determines where to send thedata using the IC 112 or the like, generates data for transmission(electric signal for transmission), and transmits the data tocorresponding optical module 102 through the printed circuit board 111.

The optical module 102 is a transceiver having a function oftransmission and reception. The optical module 102 includes a printedcircuit board 121, an optical receiver module 123A which converts anoptical signal received through an optical fiber 103A into an electricsignal, and an optical transmitter module 123B which converts theelectric signal into an optical signal and transmits the optical signalto an optical fiber 103B. The printed circuit board 121 is connected tothe optical receiver module 123A and the optical transmitter module 123Bthrough flexible printed circuit boards 122A and 122B, respectively. Anelectric signal is transmitted from the optical receiver module 123A tothe printed circuit board 121 through the flexible printed circuit board122A, and an electric signal is transmitted from the printed circuitboard 121 to the optical transmitter module 123B through the flexibleprinted circuit board 122B. The optical module 102 and the opticaltransmission device 101 are connected through an electric port 105.

The transmission system according to the embodiment includes two or moreoptical transmission devices 101, two or more optical modules 102, andone or more optical fibers 103 (for example, optical fibers 103A, 103B).One or more optical module 102 are mounted on each optical transmissiondevice 101. The optical modules 102 respectively mounted on the twooptical transmission devices 101 are connected by the optical fiber 103.An optical module 102 connected to one optical transmission device 101converts data for transmission, in which the optical transmission device101 generates, into an optical signal and transmits the optical signalto the optical fiber 103. An optical module 102 connected to the otheroptical transmission device 101 receives the optical signal transmittedover the optical fiber 103, converts the optical signal into an electricsignal, and transmits the electric signal to the other opticaltransmission device 101 as data for reception.

Here, a bit rate of the electric signal, which is transmitted andreceived by each optical module 102, is 100 Gbit/s. The opticaltransmitter module 123B multiplexes four wavelengths of light of 25Gbit/s with wavelength spacing of approximately 20 nm and transmits themultiplexed signal at 100 Gbit/s using a coarse wavelength divisionmultiplexing (CWDM) method.

FIG. 2 is a plan view illustrating a configuration of the opticaltransmitter module 123B according to the embodiment. The opticaltransmitter module 123B includes an outer case 10, an arrayedsemiconductor optical device 11 (a plurality of semiconductor opticaldevices 12 are mounted on an arrayed semiconductor optical device 11),an optical component 14 on which a plurality of collective lens aremounted, an optical multiplexer 15, and an optical fiber port 16, andthe arrayed semiconductor optical device 11 is connected to the flexibleprinted circuit board 122B. An electric signal is input to each of theplurality of semiconductor optical devices 12 of the arrayedsemiconductor optical device through the flexible printed circuit board122B. Each semiconductor optical device 12 outputs an optical signal ofa corresponding emission wavelength. In the optical component 14, theoptical signal output from each semiconductor optical device 12 iscollimated by the collective lens which is mounted on the opticalcomponent 14 and corresponds to the semiconductor optical device 12, andis multiplexed into a multiplexed optical signal by the opticalmultiplexer 15. The multiplexed optical signal is output to an opticalfiber connected to the optical fiber port 16. The optical transmittermodule according to the embodiment includes the arrayed semiconductoroptical device according to the embodiment, the optical module accordingto the embodiment includes the optical transmitter module according tothe embodiment, and the optical transmission device according to theembodiment includes the optical module according to the embodiment.

FIG. 3A and FIG. 3B are schematic diagrams illustrating semiconductormultilayer structures of the semiconductor optical device 12 accordingto the embodiment. FIG. 3A illustrates a cross section including anoptical axis direction of the semiconductor optical device 12, andschematically illustrates the semiconductor multilayer structure. FIG.3B illustrates a cross section (a surface orthogonal to the optical axisdirection) taken along a line IIIB-IIIB illustrated in FIG. 3A, andillustrates a structure of the semiconductor optical device 12.

As illustrated in FIG. 3A, the semiconductor multilayer structure of thesemiconductor optical device 12 is a structure in which an n-type InPlayer 21, an n-type lower side optical guide layer 22 a, an MQW layer 22b, a p-type upper side optical guide layer 22 c, a mesa etching stoplayer 23, an InP spacer layer 24 a, an InGaAsP grating layer 24 b, ap-type InP clad layer 25, and a p⁺-type contact layer 26 are depositedon a semi-insulating Fe-doped

InP substrate 20 in order along the deposition direction. Both then-type lower side optical guide layer 22 a and the p-type upper sideoptical guide layer 22 c are an InGaAlAs semiconductor layer. The MQWlayer 22 b is a semiconductor layer in which an InGaAlAs well layer andan InGaAlAs barrier layer are alternately deposited. The mesa etchingstop layer 23 is an InGaAsP semiconductor layer. The p⁺-type contactlayer 26 is an InGaAs semiconductor layer.

As illustrated in FIG. 3B, the semiconductor multilayer structure of thesemiconductor optical device 12 is a multistage structure which iscomposed of a first mesa structure to a third mesa structure from thesubstrate side. The first mesa structure is composed of the n-type lowerside optical guide layer 22 a, the MQW layer 22 b, the p-type upper sideoptical guide layer 22 c, and the mesa etching stop layer 23. The secondmesa structure is composed of the InP spacer layer 24 a and the InGaAsPgrating layer 24 b. The third mesa structure is composed of the p-typeInP clad layer 25 and the p⁺-type contact layer 26. Mesa width issequentially narrowed from the first mesa structure to the third mesastructure. In the first mesa structure, the mesa etching stop layer 23is formed so as to cover side surfaces and upper surfaces of the n-typelower side optical guide layer 22 a, the MQW layer 22 b, and the p-typeupper side optical guide layer 22 c.

A passivation film 27 is formed over the entire surface of thesemiconductor multilayer structure except for a portion of thereof. Ap-side electrode 31 electrically connected to the p⁺-type contact layer26 and an n-side electrode 32 electrically connected to the n-type InPlayer 21 are formed. In order to physically contact the p-side electrode31 and the p⁺-type contact layer 26, the passivation film 27 is notformed on the upper surface of the p⁺-type contact layer 26. In order tophysically contact then-side electrode 32 and the n-type InP layer 21,the passivation film 27 is not formed in a region (at least a portion ofthe region) of the upper surface of the n-type InP layer 21 on which then-side electrode 32 is formed.

Here, the first semiconductor layer 22 includes the n-type lower sideoptical guide layer 22 a, the MQW layer 22 b, and the p-type upper sideoptical guide layer 22 c. In the embodiment, the first semiconductorlayer 22 is composed of the n-type lower side optical guide layer 22 a,the MQW layer 22 b, and the p-type upper side optical guide layer 22 c.The second semiconductor layer 24 includes the InP spacer layer 24 a,the InGaAsP grating layer 24 b, and an InP cap layer 24 c describedbelow. In the embodiment, the second semiconductor layer 24 is composedof the InP spacer layer 24 a, the InGaAsP grating layer 24 b, and theInP cap layer 24 c.

FIG. 4A is a schematic diagram illustrating a structure of the arrayedsemiconductor optical device 11 according to the embodiment. The arrayedsemiconductor optical device 11 according to the embodiment is afour-channel multiple wavelength laser device array, and each of thesemiconductor optical devices 12 is a ridge structure type and directmodulation type semiconductor laser device, specifically, a DFB laser.As illustrated in FIG. 4A, the arrayed semiconductor optical device 11includes a first semiconductor optical device CH1, a secondsemiconductor optical device CH2, a third semiconductor optical deviceCH3, and a fourth semiconductor optical device CH4. Each semiconductoroptical device 12 in each channel has the structure illustrated in FIG.3B. FIG. 4B illustrates main portions of semiconductor multilayerstructures of the first semiconductor optical device CH1 to the fourthsemiconductor optical device CH4, respectively. The first semiconductorlayers 22 of each semiconductor optical device 12 are deposited bySelective-Area-Growth (SAG method), a layer thicknesses of the firstsemiconductor layers 22 are sequentially increased from the firstsemiconductor optical device CH1 to the fourth semiconductor opticaldevice CH4, and emission wavelengths (gain peaks) of the firstsemiconductor layers 22 are sequentially increased from the firstsemiconductor optical device CH1 to the fourth semiconductor opticaldevice CH4. The layer thicknesses of the first semiconductor layers 22of the first semiconductor optical device CH1 to the fourthsemiconductor optical device CH4 correspond to the distance from H0which is a height of the lower surface of the first semiconductor layerto h1 to h4, respectively. Accordingly, heights of the upper surfaces ofthe first semiconductor layers 22 are sequentially increased from thefirst semiconductor optical device CH1 to the fourth semiconductoroptical device CH4 and from h1 to h4. Since the mesa etching stop layer23 and the second semiconductor layer 24 are simultaneously deposited ina process common to the first semiconductor optical device CH1 to thefourth semiconductor optical device CH4, a layer thickness of the mesaetching stop layer 23 is substantially same in the first semiconductoroptical device CH1 to the fourth semiconductor optical device CH4, and alayer thickness of the second semiconductor layer 24 is substantiallysame in the first semiconductor optical device CH1 to the fourthsemiconductor optical device CH4. Accordingly, a height of the uppersurface of the InGaAsP grating layer 24 b (height of the upper surfaceof the second semiconductor layer 24) is sequentially increased from thefirst semiconductor optical device CH1 to the fourth semiconductoroptical device CH4 and from H1 to H4.

The features of the present invention may be an arrayed semiconductoroptical device in which a plurality of semiconductor optical devicesincluding a first semiconductor optical device and a secondsemiconductor optical device are monolithically integrated on asemiconductor substrate, that each of the semiconductor optical devicesincludes a first semiconductor layer having a multiple quantum welllayer and a grating layer disposed on the upper side of the firstsemiconductor layer, and that a layer thickness of the firstsemiconductor layer of the first semiconductor optical device is thinnerthan a layer thickness of the first semiconductor layer of the secondsemiconductor optical device and the height of the grating layer of thefirst semiconductor optical device is lower than the height of thegrating layer of the second semiconductor optical device correspondingto difference in the layer thickness of the first semiconductor layer.The height of the grating layer referred to here is defined as a heightalong the deposition direction (vertical direction to a substratesurface) from the upper surface of the InP substrate 20. It is desirablethat the first semiconductor layer of each of the semiconductor opticaldevices further includes a lower side optical guide layer disposed incontact with a lower side of the multiple quantum well layer and theupper side optical guide layer disposed in contact with the upper sideof the multiple quantum well layer. It is further desirable that thefirst semiconductor layer of each of the semiconductor optical devicesis composed of a lower side optical guide layer, a multiple quantum welllayer, and the upper side optical guide layer.

In the embodiment, as described below, first semiconductor layers aredeposited by Selective-Area-Growth (SAG) and the layer thicknesses ofthe first semiconductor layers are different from each other in thefirst semiconductor optical device CH1 to the fourth semiconductoroptical device CH4. On the other hand, since the etching stop layer andthe second semiconductor layer are simultaneously deposited by a samecrystal growth process under common conditions, a layer thickness of theetching stop layer is substantially the same and a layer thickness ofthe second semiconductor layer is also substantially the same in thefirst semiconductor optical device CH1 to the fourth semiconductoroptical device CH4. Accordingly, difference in heights between thegrating layer of the first semiconductor optical device and the gratinglayer of the second semiconductor optical device is substantialdifference in the layer thickness of the first semiconductor layer. Itis further desirable that each semiconductor optical device includes theetching stop layer disposed between the first semiconductor layer andthe grating layer. In a plurality of semiconductor optical devices, whena layer thickness of certain semiconductor layers is same each other, itindicates that the semiconductor layers are simultaneously deposited bya same crystal growth process under common conditions, so that the layerthicknesses of the semiconductor layers in the crystal growth processare substantially same. That is, it means that the layer thicknesses ofthe semiconductor layers are same within in-plane distribution of thesemiconductor layers by the crystal growth process.

Increase of the transmission capacity of information is required due tothe explosive growth of the Internet population in recent years, and itis expected that optical communication will still play an important rolein the future. A semiconductor laser device is used as a light sourcefor transmission in the optical communication and is mounted on astandardized package as an optical module together with an electriccircuit for driving a device and the like. At present, transmissioncapacity of an optical module has already reached 100 Gbit/s. As in thecase of the arrayed semiconductor optical device 11 according to theembodiment, transmission capacity of 100 Gbit/s is realized by arrayingfour semiconductor optical devices (four channels) operating at 25Gbit/s and having mutually different emission wavelengths. Atransmission speed of each semiconductor optical device reaches 25Gbit/s and is thought to be a performance close to the limit of thedevice. So, it is technically not easy to further increase thetransmission speed in a short period of time. Accordingly, for largecapacity of an optical module, it is considered that a method whicharrays semiconductor optical devices having a plurality of channels (npieces) and mounts the arrayed semiconductor optical device on anoptical module is desirable to increase transmission capacity (by ntimes) in the future. The arrayed semiconductor optical device accordingto the embodiment has an optimum structure to fulfill the demand forlarge capacity and small size of the arrayed semiconductor opticaldevice.

On the other hand, in an optical transmission device used in a datacenter or the like, since a space of an optical module mounted on theoptical transmission device is limited, it is also important to improvetransmission density. For such purpose, it is desirable to increase thenumber of optical modules mounted on the same space by miniaturizing theoptical module itself. Accordingly, demands for miniaturizing of opticalmodules are rapidly increasing. The optical module and the opticaltransmission device according to the embodiment have optimum structuresto fulfill the demand for large capacity and small size of the opticalmodule.

FIG. 5 is a graph illustrating an absolute value of a change rate ofcoupling coefficient κ with respect to an increase rate of a layerthickness in a first semiconductor layer and a grating layer of asemiconductor optical device. It is generally known that performance ofa grating is represented by a product κL of coupling coefficient κ andcavity length L. The κ is proportional to difference in effectiverefractive index between a region in which the grating layer is presentand a region in which the grating layer is not present. Here, it isassumed that the semiconductor optical device has a standard devicestructure, and four channels (four) semiconductor optical devices areintegrated in an arrayed semiconductor optical device.

In the semiconductor optical device fabricated by Selective-Area-Growthillustrated in JP 07-226563A, the first semiconductor layer and thegrating layer are continuously deposited by Selective-Area-Growth, andboth the layer thickness of the first semiconductor layer and the layerthickness of the grating layer increase between channels. In this case,the absolute value of the change rate of the κ varies significantly asillustrated by the broken line in FIG. 5, and the inventors haveobtained findings that the device performance varies between thechannels. Difference in the absolute value of the change rate of the κis the largest between the first semiconductor optical device CH1 andthe fourth semiconductor optical device CH4 in which both difference inthe layer thickness of the first semiconductor layer and difference inlayer thickness of the grating layer are maximized, and difference inthe device performance also becomes large. The wavelength change ofSelective-Area-Growth is caused by the increase in the layer thicknessin principal, and it is not easy to reduce the change of the κ.

On the other hand, in the semiconductor optical device according to theembodiment, since the layer thicknesses of the grating layers aresubstantially constant between channels, only layer thicknesses of thefirst semiconductor layers increase between channels. In this case, theabsolute value of the change rate of the κ becomes smaller as a solidline illustrated in FIG. 5 as compared with the case where both thelayer thickness of the first semiconductor layer and the layer thicknessof the grating layer increase (broken line). The change rate of the κ isestimated to be substantially negligible until the increase rate of thelayer thickness of the first semiconductor layer is about 1.2 times.Since the change in layer thickness in the grating layer having a highrefractive index is suppressed, the amount of change in the refractiveindex of the entire semiconductor multilayer structure can besignificantly reduced. As a result, a variation of the change rate ofthe κ between channels can be reduced as compared with the prior art,and variations in device performance between the channels can besuppressed.

In the arrayed semiconductor optical device according to the embodiment,since the layer thicknesses of the grating layers are substantiallyconstant between channels, the semiconductor optical device can befabricated with high accuracy as compared with the case where the firstsemiconductor layer and the grating layer are continuously deposited byconventional Selective-Area-Growth, and it is possible to furthersuppress the variations in device performance between the channels.Hereinafter, this will be described.

In a case where an InP semiconductor substrate is used, a grating layeris formed of a quaternary alloy layer such as InGaAsP or InGaAlAs, andis buried in an InP layer. A manufacturing process of a semiconductoroptical device includes an etching process of the grating layer(typically, a quaternary alloy layer having a layer thickness of severaltens of nanometers). According to the conventionalSelective-Area-Growth, the layer thicknesses of the grating layers aredifferent between channels so that etching conditions are differentbetween channels. Therefore, it is difficult to simultaneously formgratings having desired pitches and shapes in the semiconductor opticaldevices of all the channels by a common etching process. When differencein the layer thicknesses of the grating layers becomes large betweenchannels, it is more difficult to fabricate uniform grating. Thenonuniformity of the shapes of the gratings is a cause of increasingvariation in device performance between the channels. It is possible toperform etching under each optimum etching conditions for each channelby several etching steps. However, in this case, the number of processesinvolved in etching increases, which is undesirable from the viewpointof cost reduction. In the arrayed semiconductor optical device accordingto the embodiment, the layer thicknesses of the grating layers aresubstantially constant between channels and the gratings can besimultaneously formed by a common etching process. The shapes of thegratings can be formed more uniformly, and the manufacturing cost canalso be reduced.

The structure of the arrayed semiconductor optical device 11 accordingto the embodiment has been described above. Next, a manufacturing methodof the arrayed semiconductor optical device 11 according to theembodiment will be described. MOVPE is used as a crystal growth methodof a semiconductor layer. Hydrogen is used as a carrier gas. Either oneof triethylgallium (TEG), trimethylindium (TMI), or trimethylaluminum(TMA), or a combination thereof is used as a source material of thegroup III element. Either one of arsine (AsH₃) or phosphine (PH₃), or acombination thereof is used as a source material of the group V element.Disilane (Si₂H₆) is used as a source material of the n-type dopant.Dimethylzinc (DMZn) is used as a source material of the p-type dopant.Cyclopentadienyl magnesium (Cp₂Mg) is also used as a source material ofthe p-type dopant. The manufacturing method of the optical transmittermodule according to the embodiment is realized by mounting the arrayedsemiconductor optical device according to the embodiment using a knownmounting method. The manufacturing method of the optical moduleaccording to the embodiment is realized by mounting the opticaltransmitter module according to the embodiment using a known mountingmethod. The manufacturing method of the optical transmission deviceaccording to the embodiment is realized by mounting the optical moduleaccording to the embodiment using a known mounting method.

The crystal growth method is not limited to MOVPE. It goes withoutsaying that the effect of the present invention can be obtained usingMolecular Beam Epitaxy (MBE), Chemical Beam Epitaxy (CBE), Metal-organicMolecular Beam Epitaxy (MOMBE), or the like as long as the samestructure can be manufactured by these methods. Materials other thanabove-mentioned source materials may also be used as materials of groupIII, group V, dopants, and the like.

FIGS. 6A to 6L are diagrams illustrating a process of the manufacturingmethod of the arrayed semiconductor optical device 11 according to theembodiment. The n-type InP layer 21 is formed on the Fe-doped InPsubstrate 20. A pair of the insulator masks 41 for each channel (a totalof four pairs of insulator masks 41) is formed on the upper surface ofthe n-type InP layer 21 so as to realize a desired wavelength change(insulator mask forming process: FIG. 6A). The pair of the insulatormasks 41 is disposed so as to sandwich a region where the firstsemiconductor layer 22 to be disposed in a later process. The emissionwavelength of the MQW layer 22 b of the first semiconductor layer 22depends on spacing (opening) of the pair of the insulator masks 41 andmask width. Accordingly, the spacing of the pair of the insulator masks41 and the mask width for each channel are determined such that thelayer thickness of the first semiconductor layer 22 increases from thefirst semiconductor optical device CH1 to the fourth semiconductoroptical device CH4.

The first semiconductor layer 22 is deposited on the Fe-doped InPsubstrate 20 (SAG growth process: FIG. 6B). In the SAG growth process,although a protective layer (InP cap layer) is usually deposited on theupper side of the first semiconductor layer 22, it is omitted toillustrate in FIG. 6B. The layer thickness of the first semiconductorlayer 22 increases from the first semiconductor optical device CH1 tothe fourth semiconductor optical device CH4 by the pair of insulatormasks 41 of each channel. That is, the first semiconductor layer 22 ofthe first semiconductor optical device CH1 and the first semiconductorlayer 22 of the second semiconductor optical device CH2 aresimultaneously deposited such that the layer thickness of the firstsemiconductor layer 22 of the first semiconductor optical device CH1 isthinner than that of the first semiconductor layer 22 of the secondsemiconductor optical device CH2. The first semiconductor layerdeposition process according to the embodiment includes the insulatormask forming process and the SAG growth process. In addition to thefirst semiconductor layer 22 of each channel, a dummy semiconductorlayer 42 is simultaneously formed in each region between the channels.

The pair of the insulator masks 41 of each channel and the dummysemiconductor layer 42 formed in each region between channels areremoved (insulator mask removing process: FIG. 6C). The protective layerdeposited on the upper side of the first semiconductor layer 22 isremoved before the etching stop layer deposition process is performed.

The mesa etching stop layer 23 (etching stop layer deposition process)and the second semiconductor layer 24 (grating layer deposition process)are continuously deposited on the Fe-doped InP substrate 20 so as tocover the first semiconductor layer 22 (FIG. 6D). The mesa etching stoplayer 23 and the second semiconductor layer 24 are formed over theentire surface of the Fe-doped InP substrate 20. The mesa etching stoplayer 23 is deposited to form the first mesa structure. Since the mesaetching stop layer 23 of the semiconductor optical device 12 of eachchannel can be formed under a same growth condition, the layer thicknessof the mesa etching stop layer 23 of each channel is substantially same.Each of the second semiconductor layers 24 of the first semiconductoroptical device CH1 to the fourth semiconductor optical device CH4 issimultaneously deposited under common growth conditions. Since thesecond semiconductor layers 24 of the semiconductor optical device 12 ofeach channel can be formed under the same growth condition, the layerthickness of the second semiconductor layers 24 of each channel issubstantially same.

FIG. 6E illustrates a structure of one semiconductor optical device 12among the arrayed semiconductor optical devices 11 illustrated in FIG.6D. FIG. 6E on the left side illustrates a cross section perpendicularto the optical axis direction similarly to FIG. 6D. FIG. 6E on the rightside illustrates a cross section including the optical axis directionsimilarly to FIG. 3A. The same applies to FIGS. 6F to 6I. As illustratedin FIG. 6E, the second semiconductor layer 24 includes the InP spacerlayer 24 a, the InGaAsP grating layer 24 b, and the InP cap layer 24 c.

The oxide mask 43, which is a grating pattern mask, is formed in theupper portion of a region of the InGaAsP grating layer 24 b formed overthe entire surface in which the MQW layer 22 b forms as an opticalwaveguide in each channel (grating pattern mask forming process: FIG.6F). The oxide mask 43 is deposited and the deposited oxide mask 43 isprocessed into a grating pattern having a periodic structure byinterference exposure method, electron beam exposure method, or thelike. As illustrated in FIG. 6F on the right side, a region in which agrating is formed and a region in which a grating is not formed areperiodically repeated along the optical axis direction and forms thegrating pattern.

The InP cap layer 24 c is etched using the oxide mask 43 as a mask (InPcap layer etching process: FIG. 6G). As illustrated in FIG. 6G, etchingconditions are adjusted such that etching stops at the upper surface ofthe InGaAsP grating layer 24 b. Next, the oxide mask 43 is removed(oxide mask removing process: FIG. 6H).

The InGaAsP grating layer 24 b is etched using the InP cap layer 24 c asa mask and a grating is formed (grating forming process: FIG. 6I). Atthis time, etching conditions are adjusted such that the InP spacerlayer 24 a functions as an etching stop layer and etching stops at theupper surface of the InP spacer layer 24 a. In this process, the secondmesa structure is formed.

The p-type InP clad layer 25 and the p⁺-type contact layer 26 arecontinuously deposited over the entire surface of the Fe-doped InPsubstrate 20 (upper side clad layer deposition process: FIG. 6J). Inthis process, all the crystal growth processes are completed. At thistime, since the InP cap layer 24 c disposed on the InGaAsP grating layer24 b (grating) is integrated with the p-type InP clad layer 25, the InPcap layer 24 c is not illustrated. Similarly, since the InP spacer layer24 a is also integrated with the p-type InP clad layer 25, the InPspacer layer 24 a is not illustrated. The InP spacer layer 24 a isformed under the InGaAsP grating layer 24 b, and the InP spacer layer 24a and the InGaAsP grating layer 24 b in this portion are illustrated asthe second semiconductor layer 24.

A mask is formed on the upper surface of the p⁺-type contact layer 26and etching is performed using the mask to remove regions of the p⁺-typecontact layer 26 and the p-type InP clad layer 25 which exist on bothsides of the mask, thereby forming the third mesa structure (ridgestructure) (mesa forming process: FIG. 6K). An appropriate etchingmethod such as wet etching or dry etching is selected and etchingconditions are adjusted such that etching stops at the upper surface ofthe mesa etching stop layer 23. As illustrated in FIG. 3B, the etchingstops at the upper surface of the InGaAsP grating layer 24 b in a regionin which the InGaAsP grating layer 24 b is formed. In a region on thesame layer as the InGaAsP grating layer 24 b and in which InGaAsPgrating layer 24 b is not formed, the etching further proceeds and stopsat the upper surface of the mesa etching stop layer 23.

A region of the mesa etching stop layer 23 which is an outside of thefirst mesa structure is removed to expose a region of the n-type InPlayer 21 in which the n-side electrode 32 is formed (mesa etching stoplayer removing process: FIG. 6L). The n-type InP layers 22, which areformed in regions between channels, are removed to electrically isolatethe channels, and the upper portion of the Fe-doped InP substrate 20 inthe region is removed to reach the inside of the Fe-doped InP substrate20. The passivation film 27 is formed over the entire surface of theFe-doped InP substrate 20. The passivation film 27 existed on the uppersurface of the p⁺-type contact layer 26, which is a contact portion ofthe p-side electrode 31 and at a contact portion with n-side electrode32 in the upper surface of the exposed n-type InP layer 21 is removed toform the p-side electrode 31 and the n-side electrode 32, and waferprocesses are completed. The arrayed semiconductor optical device 11according to the embodiment is fabricated by cleaving from the wafer.

In the arrayed semiconductor optical device 11 fabricated in thismanner, since adjacent channels are electrically insulated, differentialdrive is possible. When device performance of the arrayed semiconductoroptical device 11 is characterized, variations in threshold current andslope efficiency at high temperature operation between the four channelsare small, and the modulation characteristic under 25 Gbit/s operationis also good.

Second Embodiment

The arrayed semiconductor optical device 11 according to a secondembodiment of the present invention is, similarly to the firstembodiment, a ridge structure type four-channel multiple wavelengthlaser device array, and each semiconductor optical device 12 is asemiconductor laser device that outputs a continuous wave (CW),specifically, a DFB laser. A plurality of electro-absorption (EA)modulators that modulate and output the continuous waves from each ofthe plurality of the semiconductor optical devices 12 are alsomonolithically integrated into the arrayed semiconductor optical device11. That is, each semiconductor optical device 12 is a laser portion ofthe EA modulator integrated DFB laser. The arrayed semiconductor opticaldevice 11 according to the first embodiment includes the Fe-doped InPsubstrate 20, and the n-side electrode 32 is formed on the same sidewith respect to the p-side electrode 31 and the semiconductor substrate.On the other hand, the arrayed semiconductor optical device 11 accordingto the embodiment includes an n-type InP substrate 50, and an n-sideelectrode 62 is formed on the opposite side to a p-side electrode 61with respect to the semiconductor substrate. Accordingly, asemiconductor multilayer structure of each semiconductor optical device12 is different from that of the first embodiment, but other structuresare the same as that of the first embodiment.

FIG. 7 is a schematic diagram illustrating a structure of the arrayedsemiconductor optical device 11 according to the embodiment. In thesemiconductor multilayer structure of the semiconductor optical device12, an n-type lower side optical guide layer 52 a, an MQW layer 52 b, ap-type upper side optical guide layer 52 c, a mesa etching stop layer53, an InP spacer layer 54 a, an InGaAsP grating layer 54 b, a p-typeInP clad layer 55, and p⁺-type contact layer 56 are deposited on then-type InP substrate 50 in order along the growth direction. Both then-type lower side optical guide layer 52 a and the p-type upper sideoptical guide layer 52 c are an InGaAsP semiconductor layer. The MQWlayer 52 b is a semiconductor layer in which an InGaAsP well layer andan InGaAsP barrier layer are alternately deposited. The mesa etchingstop layer 53 is the InGaAsP semiconductor layer. The p⁺-type contactlayer 56 is an InGaAs semiconductor layer. The first semiconductor layer52, similarly to the first embodiment, includes an n-type lower sideoptical guide layer 52 a, an MQW layer 52 b, and a p-type upper sideoptical guide layer 52 c, and the second semiconductor layer 54 includesan InP spacer layer 54 a, an InGaAsP grating layer 54 b, and an InP caplayer (not illustrated). A bank portion 59, which is simultaneouslydeposited in a crystal growth process of the p-type InP clad layer 55(and the p⁺-type contact layer 56), is disposed on one side (left sideof FIG. 7) of each semiconductor optical device 12. The p⁺-type contactlayer 56 is also formed on the uppermost layer of the bank portion 59,but it is removed before a passivation film 57 described later isformed. The passivation film 57 is formed over the entire surface of then-type InP substrate 50 except for the upper surface of the p⁺-typecontact layer 56 which is a contact portion of the p-side electrode 61.The p-side electrode 61 is in contact with the upper surface of thep⁺-type contact layer 56, and extends to one side of each semiconductoroptical device 12 to form a pad portion on the upper surface of the bankportion 59. Further, the n-side electrode 62 is formed on a back surfaceof the n-type InP substrate 50.

In a manufacturing method of the arrayed semiconductor optical device 11according to the embodiment, since the characteristic processesaccording to the present invention are common with the manufacturingmethod of the arrayed semiconductor optical device 11 according to thefirst embodiment, details will be omitted. In a case where the thirdmesa structure (ridge structure) of the semiconductor multilayerstructure is formed by etching, etching conditions are adjusted suchthat the etching stops at the upper surface of the mesa etching stoplayer 53. Between the third mesa structure (ridge structure) of thesemiconductor multilayer structure and the bank portion 59 (pad portionof p-side electrode 61) may be planarized with polyimide, BCB, or thelike.

Ground potential (ground) in each channel of the arrayed semiconductoroptical device 11 according to the embodiment is the n-type InPsubstrate 50 (and the n-side electrode 62), which is common for allchannels. The arrayed semiconductor optical device 11 fabricated in thismanner can be used as a CW light source. When device performance of thearrayed semiconductor optical device 11 is characterized, variations inthreshold current and slope efficiency at high temperature operationbetween the four channels are small, and it is possible to reducevariation in optical output between channels. Here, although the arrayedsemiconductor optical device 11 according to the embodiment includes then-type InP substrate 50, the arrayed semiconductor optical device 11according to the embodiment is not limited to this and may include ap-type InP substrate.

Third Embodiment

An arrayed semiconductor optical device 11 according to a thirdembodiment of the invention is, similarly to the first embodiment, afour-channel multiple wavelength laser device array, and eachsemiconductor optical device 12 is a buried hetero structure type anddirect modulation type semiconductor laser device, specifically, a DFBlaser. By employing the buried hetero structure type, a semiconductormultilayer structure of semiconductor optical device 12 according to theembodiment is different from that of the first embodiment and a shape ofthe p-side electrode 31 is also different from that of the firstembodiment, but other structures are the same as that of the firstembodiment.

FIG. 8 is a schematic diagram illustrating a structure of the arrayedsemiconductor optical device 11 according to the embodiment. In thesemiconductor multilayer structure of the semiconductor optical device12 according to the embodiment, an n-type InP layer 21, an n-type lowerside optical guide layer 22 a, an MQW layer 22 b, a p-type upper sideoptical guide layer 22 c, an InP spacer layer 24 a, an InGaAsP gratinglayer 24 b, a p-type InP clad layer 25, and a p⁺-type contact layer 26are deposited on an Fe-doped InP substrate 20 in order along the growthdirection. The mesa etching stop layer 23, which is deposited betweenthe first semiconductor layer 22 and the second semiconductor layer 24in the first embodiment, is not deposited in the embodiment.

In the first embodiment, the semiconductor multilayer structure is themultistage structure. However, in the embodiment, the semiconductormultilayer structure placed on both sides of a region of the MQW layer22 b in which an optical waveguide is formed is removed from the p³⁰-type contact layer 26 to the n-type InP layer 21, thereby forming amesa stripe structure. The both sides of the mesa stripe structure areburied with a buried layer 28. Here, the buried layer 28 is asemi-insulating InP layer in which iron (Fe) is doped and ferrocene isused as an organometallic source material of iron. The buried layer 28may be a semi-insulating InP layer in which ruthenium (Ru) is doped.

In the arrayed semiconductor optical device 11 fabricated in thismanner, since adjacent channels are electrically isolated, differentialdrive is possible. When device performance of the arrayed semiconductoroptical device 11 is characterized, variations in threshold current andslope efficiency at high temperature operation between the four channelsare small, and the modulation characteristic under 25 Gbit/s operationis also good.

The semiconductor optical device, the arrayed semiconductor opticaldevice, the optical transmitter module, the optical module, the opticaltransmission device, and the method for manufacturing thereof accordingto embodiments of the invention have been described above. In the aboveembodiments, a direct modulation laser and a CW DFBlaser are describedas examples of the semiconductor optical device, but it goes withoutsaying that the semiconductor optical device is not limited to these andit is widely applicable to a semiconductor optical device includinggrating on the upper side of the first semiconductor layer. The mesaetching stop layer may be provided if necessary, and a mesa formationmay be performed by using the grating layer as a mesa etching stoplayer. Further, the present invention is not limited to the four-channelarray and is applicable as long as it is an array device in which two ormore semiconductor optical devices 12 are integrated. In the arrayedsemiconductor optical device according to the above embodiments, the InPsemiconductor substrate is used, but the substrate is not limited tothis and other semiconductor substrates may be used. The firstsemiconductor layer according to the above embodiments has a three-layerstructure including the lower side optical guide layer, the MQW layer,and the upper side optical guide layer, but the structure is not limitedto this. As necessary, the first semiconductor layer according to theabove embodiments may have only the MQW layer or may have a structure inwhich a semiconductor layer is further deposited in addition to thethree layers.

The first semiconductor layer of the semiconductor optical device isdeposited by Selective-Area-Growth (SAG), and the second semiconductorlayer is simultaneously deposited by a common process between channels,but the crystal growth method of the first semiconductor layer is notlimited to Selective-Area-Growth. Other crystal growth methods areapplicable as long as the layer thickness of the first semiconductorlayer of the first semiconductor optical device can be simultaneouslydeposited as being thinner than the layer thickness of the firstsemiconductor layer of the second semiconductor optical device. Thearrayed semiconductor optical device having a bit rate to be transmittedof 100 Gbit/s is described as an example, but it goes without sayingthat the bit rate is not limited to this and other bit rates or symbolrates can be applied. The present invention can be widely applied.

While there have been described what are at present considered to becertain embodiments of the invention, it will be understood that variousmodifications may be made thereto, and it is intended that the appendedclaims coverall such modifications as fall within the true spirit andscope of the invention.

What is claimed is:
 1. An arrayed semiconductor optical devicecomprising: a plurality of semiconductor optical devices including afirst semiconductor optical device and a second semiconductor opticaldevice which are monolithically integrated on a semiconductor substrate,wherein each of the semiconductor optical devices includes a firstsemiconductor layer having a multiple quantum well layer and a gratinglayer disposed on an upper side of the first semiconductor layer,wherein a layer thickness of the first semiconductor layer of the firstsemiconductor optical device is thinner than a layer thickness of thefirst semiconductor layer of the second semiconductor optical device,and wherein a height of the grating layer of the first semiconductoroptical device is lower than a height of the grating layer of the secondsemiconductor optical device corresponding to difference in the layerthickness of the first semiconductor layer.
 2. The arrayed semiconductoroptical device according to claim 1, wherein the first semiconductorlayer of each of the semiconductor optical devices further includes alower side optical guide layer disposed in contact with a lower side ofthe multiple quantum well layer and an upper side optical guide layerdisposed in contact with an upper side of the multiple quantum welllayer.
 3. The arrayed semiconductor optical device according to claim 2,wherein the first semiconductor layer of each of the semiconductoroptical devices is composed of the lower side optical guide layer, themultiple quantum well layer, and the upper side optical guide layer. 4.The arrayed semiconductor optical device according to claim 1, whereindifference in heights between the grating layer of the firstsemiconductor optical device and the grating layer of the secondsemiconductor optical device is substantial difference in the layerthickness of the first semiconductor layer.
 5. The arrayed semiconductoroptical device according to claim 1, wherein each of the semiconductoroptical devices further includes an etching stop layer disposed betweenthe first semiconductor layer and the grating layer.
 6. An opticaltransmitter module comprising the arrayed semiconductor optical deviceaccording to claim
 1. 7. An optical module comprising the opticaltransmitter module according to claim
 6. 8. A method for manufacturingan arrayed semiconductor optical device including a plurality ofsemiconductor optical devices including a first semiconductor opticaldevice and a second semiconductor optical device which aremonolithically integrated on a semiconductor substrate, each of thesemiconductor optical devices including a first semiconductor layerhaving a multiple quantum well layer and a grating layer disposed on anupper side of the first semiconductor layer, the method comprising: afirst semiconductor layer deposition process of simultaneouslydepositing the first semiconductor layer of the first semiconductoroptical device and the first semiconductor layer of the secondsemiconductor optical device such that a layer thickness of the firstsemiconductor layer of the first semiconductor optical device is thinnerthan a layer thickness of the first semiconductor layer of the secondsemiconductor optical device; and a grating layer deposition process ofsimultaneously depositing the grating layer of the first semiconductoroptical device and the grating layer of the second semiconductor opticaldevice under common conditions.
 9. The method for manufacturing anarrayed semiconductor optical device according to claim 8, wherein, inthe first semiconductor layer deposition process, the firstsemiconductor layer of the first semiconductor optical device and thefirst semiconductor layer of the second semiconductor optical device aresimultaneously deposited by Selective-Area-Growth.